In a conventional PDP apparatus, for example in an operation of a reset period of sub-field drive control, ramp waves are outputted to electrodes of a PDP by ramp wave output devices (circuits).
The ramp wave output devices (ramp output devices) in the conventional PDP apparatus includes a mode such as that described in Japanese Patent Application Laid-Open Publication No. 2002-328649. This is realized by generating a ramp wave by using a capacitive load and a constant current source and outputting it via an impedance conversion circuit. This often has a circuit configuration such as that of FIG. 6 as a mode that is actually used.
In FIG. 6, in a ramp output device 900, C01 is a capacitive load, the part of E01 (voltage) and R01 (resistance) is a constant current source, and Q01 (FET: field effect transistor) performs impedance conversion. SW01 and the like are switches, Vp and the like are power sources, and SP, CU, and CD are external control inputs of the switches. The output is connected to a cell of a PDP. The right side of the ramp output device 900 is a Y output circuit of sustain waveform. The ramp output device 900 becomes active when the high level (H) of SW01 (SP) is ON as shown in FIG. 7. At that point, since the voltages of the gate and the source of Q01 are approximately the same, the voltage of E01 is applied to both ends of R01 all the time, and E01 and R01 output a constant current I=E01/R01 to C01. As a result, ramp waves are generated at both the ends of C01, and a ramp wave signal thereof is outputted via Q01. When the low level (L) of SW01 is ON, since the part between the gate and the source of Q01 is short-circuited, Q01 is caused to be in a non-operated state, and output of the ramp wave is stopped.